It is generally recognized that conventional test techniques, such as stuck-at-fault testing supplemented with IDDQ (Direct Drain Quiescent Current) testing, are ineffective in screening out timing-related defects in modern small-feature-size (e.g., 90 nm) ICs, running at frequencies that may reach the GHz range [1].
On another account, in order to enhance flexibility, IC designs with multiple clocks have become more and more popular. Most system-on-chip (SoC) designs have multiple function components and various peripheral interfaces. Components and interfaces, following different standards, often operate at different frequencies. For example, the Intel® IXP425 network processor, which is widely used in communication systems, has a processor running at 533 MHz, three network processor engines running at 133 MHz, and a variety of interfaces running at various frequencies [4]. This multi-clock trend creates a difficult challenge for at-speed testing.
Nevertheless, at-speed testing of transition faults and path-delay faults is becoming essential in many applications for testing high performance digital circuits.
Theoretically, the required at-speed test clock signals could be provided either by an external ATE (Automatic Test Equipment) or generated on chip by internal PLLs, digital dividers, or equivalent integrated high frequency generators. However, the cost of a suitable ATE tool or the cost of the IC package may become prohibitive, especially for circuits running in the GHz range.
Therefore, there is a quest for a clock control in the test structure that would make it possible to carry out at-speed testing using a relatively low-speed ATE.
The concept of such a clock control is to use on-chip clock sources, such as, for example, PLLs or digital dividers, to provide at-speed test pulses, while the ATE tool provides shift pulses and test control signals of slower speed. On-chip-test-clock generation is economical and is utilized in many industry designs [2-3].
Many methods have been proposed to address the aggravation of the technical problems created by the presence of an increasing number of distinct clock domains. Publications [5] and [6] disclose an at-speed testing architecture for multi-clock-domain ICs, based on built-in self-test (BIST) logic; [7] discloses a control scheme for inter-clock at-speed testing. These control schemes may efficiently test the timing-related faults between clocks, but need additional logic to support intra-clock at-speed testing, thus increasing the area overhead. Moreover, these known schemes may generate only one type of test-clock pair, which means that they may not be flexible enough to support efficient ATPG (Automatic Test Pattern Generation) software techniques.
U.S. Pat. No. 4,503,537, which is incorporated by reference, describes a basic infrastructure for built-in self-test of digital ICs. A linear feedback shift register (LFSR) generates random patterns. A multi-input shift register (MISR) is used to collect and compact test responses. Multiple parallel scan chains are coupled between the LFSR and MISR for inserting test vectors into the circuit under test and for capturing the results. A BIST controller coordinates the loading of scan chains with pseudorandom patterns from the generator. After the loading of a pseudorandom pattern is completed, a single capture clock is applied to capture the responses into the scan chains. Subsequently, the responses are shifted out and compressed into a signature. The well-known scan technique wherein scan chains are implemented in a digital circuit design by dividing the design into combinational and sequential logic is used.
The sequential logic is used to form scan cells that can be configured into scan chains during testing of the circuit. Test stimulus in the form of a test vector of data is brought in from a source such as a PRPG and clocked into the scan chain. In capture mode, data is propagated from input scan cells through functional paths of the combinational logic and captured in output scan cells (which may be the same as or different from the input scan cells). Capture mode exercises the logic's functional paths and hence tests for faults in these structures. After capture, the scan enable changes the cell operation back to scan mode and the captured data is shifted out into a response compactor such as a multiple input signature register (MISR). While the response is shifted out for one scan vector, input data is shifted in for the next scan vector. Shift in and shift out become parallel operations. After the last scan vector is shifted into the MISR, a signature is obtained in the MISR. This signature is compared with a fault-free signature to determine if the digital circuit is fault-free.
Basically, two operations are performed in both BIST and SCAN architectures, namely: scan and capture. The scan operation shifts test data into a scan chain. Once there, the test data is available in the scan chain for propagation through the circuit. The capture operation then captures the test data response after the data has propagated through the circuit, normally within one clock cycle of the digital circuit's clock. The scan operation then shifts the response out of the scan chain. The quality of at-speed testing is determined by two or more edges of the functional clock. The clock edge at which the last shift occurs is the update edge. The update edge applies the test vector to the combinational logic. The capture edge is the clock edge at which the memory elements capture the test vector response. If one or more to-be-tested sequential elements within the logic core are not initialized during the scan operation, then more edges of the functional clock may be needed to initialize and test all circuit elements. Typically, this happens when the sequential elements are not included in any scan chain (e.g., flip-flop or latch), or are memory elements instantiated within the logic core (e.g., RAM modules).
An alternative scheme uses the capture clock to provide both update and capture edges. The minimum time between an update edge and a following capture edge is the time allowed for the data to propagate through the combinational logic. This time window is termed the “at-speed path”.
According to the method disclosed in the above-mentioned patent, all scan chains are assumed to operate at the same frequency. If the circuit has multiple frequencies, it has to operate at the slowest frequency to allow enough time for signals in those slow domains to propagate reliably to steady states before they are captured. The transitions are generated by the last shift in every loading sequence. All responses are captured simultaneously.
Reference [8] discloses a clock-chain-based clock-control scheme adapted to efficiently test delay faults in intra-clock domain in an industry design running at 1 GHz, and [9] discloses an improved clock-chain-based clock-control scheme for multi-clock at-speed testing adapted to generate various test clock sequences for both inter-clock domain and intra-clock domain at-speed testing having a reduced area requirement with an increasing number of clock domains.
Another viable SCAN technique and implementing architecture adapted to effectively cope with the technical problem of at-speed testing of multi-clock-domain ICs is disclosed in the paper “Automatic Insertion Flow of On Chip Controller for At-Speed Testing”, by Franco Cesari and Salvatore Talluto, presented at the SNUG Europe 2007 Conference, and in the successive paper “Full Hierarchical Flow for Custom On-Chip Controller and Scan Compression Insertion for At-Speed Testing”, by Franco Cesari, Salvatore Talluto, Alfredo Conte, and Paolo Giovacchini, presented at the SNUG Europe 2008 Conference, the whole contents of which are incorporated by reference.
The SCAN architecture described in these publications is based on the insertion of dedicated-clock sourcing circuits, named OCCs (acronym for on-chip clock), at least one, and more likely several, for each clock domain of the multi-clock-domain IC.
These OCCs are finite state machines, the function of which is that of sourcing the respective test clock signals to the digital circuits of the domain, both those generated by the external ATE being used for the test, typically when carrying out conventional stuck-at faults checks, that may be supplemented by IDDQ (direct drain quiescent current) tests, and those generated internally by suitable integrated clock generators, for example PLLs, digital dividers, and alike functional circuits for at-speed testing for time-related faults such as transition faults (TF) and path-delay faults.
Defectiveness of multi-clock-domain digital ICs is measured by a calculated DPPM value on the basis of process yield and test coverage of the integrated devices. The DPPM value reflects the number of failures activated by the test program, which corresponds to the sum of failures due to different overall defect types.
As already mentioned, a particularly elusive type of defect are the transition faults (TF), and according to present day “at-speed” multiple-clock-domains digital-IC-testing techniques, TFs are normally tested “intra-domain” using the IEEE 1450 Standard test language, whilst “inter-domain” at-speed testing of transition fails remains the responsibility of the designer of the ICs, who has to guarantee two main test conditions, namely;                a) internal at-speed clocks phase predictability and coherently with the external test signals (ATE clocks, scan enable, etc.);        b) respect of the test cycle described in the Standard protocol.        